This invention relates to circuitry and methods for efficient first-in-first-out (FIFO) memory. FIFO memory is one type of memory that can be used to temporarily store or buffer data. FIFO memory is especially useful for translating data between different frequency domains. A first circuit can write data to the FIFO at a first data rate and a second circuit can read the data from the FIFO at a second data rate. Both circuits can access the FIFO in their respective frequency domains and transfer data between their respective frequencies without any real coordination or handshaking between the domains.
Typical FIFO memories are able to read and write data every clock cycle. Accordingly, typical FIFO memories are often built from dual-port memory cells that allow the simultaneous reading and writing of data to the memory. Dual-port memory cell FIFO memories are larger and more complex than standard memory cells.
It would therefore be desirable to provide circuitry and methods for an efficient FIFO memory that provides the speed and versatility of two-port memory based FIFO memory, but that has a reduced size, reduced power consumption, and increased speed.